Asynchronous circuits

Abstract

J. Cortadella first presented asynchronous circuits. The idea is to replace the global synchronization achieved by the clock with a local, joint synchronization of data and control. There are two variants, briefly described here.

Dual-rail encoding encodes any data on two wires, the value pairs 0,1>, 1,0> and 0,0> encoding the values 0, 1 and space respectively, the pair 1,1> being unused. Any sequence of two values must be separated by a space. A special Müller C-element gate enables parallel calculations to be synchronized. Dual rail guarantees logic operation independent of wire and gate delays: on average, it's faster than synchronous, because you can signal the end of the calculation as soon as it has occurred, instead of always waiting for the worst case. This means that n-bit numbers can be added together in _log2(_log2(n)) average time, instead of _log2(n). But this gain comes at the cost of doubling the surface area and energy, which limits this technique to specific cases.

Jordi Cortadella

Jordi Cortadella, professor at Universitat Politècnica de Catalunya in Barcelona, specializes in electronic circuit design and synthesis. He is interested in alternatives to conventional synchronous circuits, which seek to avoid their disadvantages: large-scale clock distribution is difficult and energy-intensive; excessively long wires have to be cut by registers, which greatly complicates control; finally, chips often feature several independent clocks, with communication problems between asynchronous zones that cannot be solved by synchronous methods.