Synchronous and multi-clock circuit design in Esterel v7

My team embarked on several years of development of the language, the compiler and its Esterel Studio development environment, accompanied by experiments in research or pre-industrial applications at Intel, Texas Instruments (TI), ST microelectronics and NXP (formerly Philips). Esterel Studio then went into production at TI and ST: various memory controls, including the difficult DMAs(Direct Memory Access) for data-intensive applications, bus, network-on-chip and communications management, video system control, etc.

In 2007, the language was handed over to the IEEE [1], with a view to standardization, led by a group of researchers and industrialists. Its formal rigor has enabled circuits to be developed faster, with fewer engineers and, above all, verifiers, while maintaining excellent efficiency. This language has enabled architects and micro-architects to quickly test and modify their ideas using our graphical simulators and formal verification tools, while being confident in the quality of the final synthesis. In 2014, I'll be showing how the industry presented us with more difficult scientific problems than those we faced in research, and then presenting the formal verification methods for Esterel v7.

The adventure came to an end in March 2009 in the wake of the 2008 crisis, as it did for many innovative products at the time. IEEE standardization of the language, almost complete, was suspended. Esterel Studio was acquired by Synfora, which in turn was acquired by Synopsys, the industry leader. Synopsys decided to put Esterel Studio in the freezer, so that even its authors could no longer use it, whereas all the tools had previously been freely available for teaching and research.

Esterel v7, language design

Esterel v7's temporal instructions are derived from those of Esterel v5, but simplify the simultaneous or conditional transmission of signals; the modular structure has been improved and made more generic. Esterel v5's signals have also been extended to meet circuit requirements; their values and presence bits are both optional, and values can be temporary, memorized or delayed. But the main new feature is the handling of data and arrays. Esterel v7 introduces numeric types that are far more precise than those of the usual languages, such as the unsigned type, which denotes the set of M natural integers i such that 0 ≤ i < M, and the signed type, which denotes the set of 2M signed integers i such that -M ≤ i < M. There are several reasons for introducing these types. Firstly, in circuits, reasoning on the size in number of bits of binary writing is insufficient: for example, we have the typings 4: unsigned<5>, 5: unsigned<6> and 4*5 = 20: unsigned<21>. If 4 and 5 are written with 3 bits in binary, their product 20 is written with 5 bits, and not the 6 obtained by adding their individual sizes; this becomes obvious thanks to the unsigned type<21>. Secondly, binary is not the only useful encoding in hardware, where we also work in Gray code, with a single bit changing at each increment, or in onehot code, with a single bit at 1 in the writing of the number. The signed and unsigned types are abstract and independent of their representations, which can have a variable number of bits. Finally, unsigned types are used to index arrays, and our typing makes it easy to test for index overflows at compile time by type analysis or formal verification.

In Esterel v7, arrays are of any type and size, and can be parametric. They apply to signals and values. A static replication instruction lets you build process arrays to manipulate data and signal arrays. Finally, Esterel v7 allows two types of clock manipulation: cycle masking(clock-gating), which has true mathematical semantics, unlike conventional Verilog/VHDL languages, and the modular use ofmultiple clocks. These aspects will be covered in more detail in 2014.

The lecture ended with the presentation of a video mini-filter that illustrates the different aspects of the language, as well as how to use it to easily "pipeline" circuits and thus reduce their cycle times.