Abstract
Elastic circuits generalize previous notions of asynchronism in a way that also applies to synchronous circuits. The idea is to give greater architectural freedom by dissociating the logical time of calculation from the physical time of realization. A classic example is GALS(Globally Asynchronous Locally Synchronous) circuits, where locally synchronous islands are connected by multi-clock synchronizers or asynchronous queues. The tricky problem here is that of register metastability (I refer to my 2013-2014 lecture).
A more recent example is that of elastic synchronous circuits. They remain synchronous, but use the valid/stop protocol of asynchronous circuits. The clock is retained and the logic design remains the same as in synchronous, but the registers are automatically replaced by pairs of transparentlatches that store their input during one phase of the clock and behave as simple wires during the other phase. The valid/stop threads are managed by an asynchronous layer that controls clock gating to inhibit the transitions of the transparent latches. Clock elasticity is thus guaranteed. Any excessively long wire can be cut by a bubble (uninitialized register) without modifying circuit control, which is impossible in synchronous design, and more elaborate pipelines can be realized. These new circuits represent a definite conceptual advance, but industrial conformism means that their success is far from guaranteed.
