Abstract
Compiling Esterel v7
Compiling Esterel v7 is a tricky business. For circuit compilation, the basic principle remained that of Esterel v5, but the technique was complicated by four factors: array processing, modular compilation of large programs, clock management, and, alas, the poor semantic quality of the target languages VHDL and Verilog. The key to ultimate success iscontrol optimization, based on algorithms originally developed for Esterel v5 and improved for Esterel v7. The idea is to symbolically calculate the space of achievable control memory states for legal inputs, then simplify the logic and reallocate control memory according to these achievable states. This optimization uses TiGeR software, mentioned above for formal verification of Esterel v5 [1]. The results in terms of circuit size and speed are comparable to those of manual designs, and often better.
Compilation in C or C++ software has become indispensable for two reasons. Firstly, it's the fastest way to test the circuit in simulation; secondly, software engineers need to develop applications before the circuit physically exists, to meet time-to-market requirements. Esterel v7 has adopted techniques developed elsewhere for Esterel v5, in particular by S. Edwards at Columbia University (USA) and D. Potop at Ecole des Mines [2]. These techniques are complex, and the lecture presented only the principle behind them. The lecture ended with a demonstration of source animation during simulation, based on source code traceability techniques in the generated code.
