Large-scale clock distribution on a chip

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Abstract

The complexity of integrated circuits has been growing exponentially for almost 45 years, and this pace is unlikely to slow down. The complexity of today's circuits enables the monolithic realization of complete computer systems called SOCs (for System On Circuit), often with multiple processors. These systems are divided into sub-systems and isochronous zones, representing the size of the blocks that can be conventionally synchronized using clocks local to each block. Isochronous zones often correspond to functional entities, to groupings of them, or even to their divisions.

Communication between these isochronous zones can be asynchronous (GALS for Globally Asynchronous and Locally Synchronous) or synchronous (GSLS for Globally Synchronous and Locally Synchronous). We won't go into detail about GALS systems, which are widely popular in the SOC world and often implemented by micro-networks known as NOCs (for Network On Circuit). The aim of this presentation is to show that, contrary to popular belief, large-scale synchronous SOCs are possible. In-phase synchronization of isochronous zone clocks offers a number of advantages, such as single-cycle communication between neighboring isochronous zones, the assurance of eliminating any risk of metastability, and the ability to warn the network operator if there is a risk of leaving the synchronous operating domain. These properties provide a platform for SOCs adapted to high-reliability applications.

To create a synchronous clocking system, an ANR HODISS project was set up by Lip6/SOC, with CEA-LETI and SupElec as partners. A synchronous clocking system has been realized in the form of a network of PLLs(Phase-Locked Loops) interconnected by phase comparators. The originality of the project lies in the entirely digital realization of the PLLs. These required the development of full-custom blocks for digital oscillator adjustment and other functions. A prototype 4 x 4 array has been produced in 65 nm CMOS, and has been running since the first batch of prototypes. A 10 x 10 array is currently under development.

The study of network topology and stabilization was resumed after the ANR project. To this end, an analogy was established between the behavior of the PLL network and the discretization of a surface defined by a damped 2D wave equation. This analogy has made it possible to compare the behavior of a large PLL array with the surface of a liquid in a vessel or lake. In the absence of disturbances, the surface of a liquid is perfectly flat, which means that the PLLs will all be exactly in phase after a stabilization period, without admitting phase errors depending on the distance between isochronous zones. Adjusting the PLL filter coefficients towards optimum damping minimizes the time taken to return to stabilization after a disturbance, as well as at start-up.

A disturbance in a body of water produces concentric waves that propagate, with attenuation, to the edges where they are reflected. The same phenomenon occurs in the PLL network. As in swimming pools, an ad hoc system (wave breaker) is used to suppress this reflection by simulating an infinite surface. This electronic wave-breaker dissociates the PLLs forming the edge of the network into a ring that fulfills two functions: improving network excitation by the reference frequency distributed around its periphery, and suppressing the reflection of disturbances on the edges of the network.

These techniques can be easily adapted to the synchronization of clocks in macroscopic systems such as GSM stations, computer servers and other distributed clocks, provided that these clocks are sufficiently stable, i.e. do not need to change their setting often.

This work would not have been possible without the close collaboration of Dimitri Galayko, senior lecturer, and doctoral students Chuan Shan and Eldar Ziabentov. All three are members of the CIAN team in the SOC department of UPMC's Lip6 laboratory.