Abstract
This first lecture in Paris will first give a brief overview of the various subjects covered in all the year's lectures. It will then focus on the tricky problems of multi-clock circuits.
Whereas twentieth-century digital circuits generally had a single clock, twenty-first-century systems-on-a-chip generally have several, in particular to clock components with different intrinsic frequencies and to reduce power consumption by reducing the speed of certain clocks according to the local load of the circuits they clock. The time relationships of these clocks can be varied: synchronized, phase-shifted, harmonic or even truly asynchronous, the latter being the most complex in terms of information exchange. Indeed, when data produced on one clock is to be read by a system clocked on another asynchronous clock, it may happen that a receiving clock edge controlling the sampling of an input by a register arrives at the moment when the input itself is changing. In this case, the register may render a random Boolean value or remain metastable between the two Boolean values for a random time. We'll be looking at two fundamental setups that use specific protocols to get around this intrinsic difficulty: multi-clock synchronizers and multi-clock FIFO queues. We'll see that these set-ups are tricky and costly, and that various seemingly clever optimizations can turn out to be radically wrong.
